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74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Rev. 5 -- 26 July 2010 Product data sheet
1. General description
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation Multiple package options Specified from -40 C to +85 C and -40 C to +125 C
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
Table 1. Ordering information Package Temperature range 74AUP1G74DC 74AUP1G74GT 74AUP1G74GF 74AUP1G74GD 74AUP1G74GM 74AUP1G74GN 74AUP1G74GS -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C Name VSSOP8 XSON8 XSON8 XSON8U XQFN8U XSON8 XSON8 Description Version plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 x 1.95 x 0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 Type number
plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 x 2 x 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT902-1 SOT1116 SOT1203
4. Marking
Table 2. Marking codes Marking code[1] p74 p74 54 p74 p74 54 54 Type number 74AUP1G74DC 74AUP1G74GT 74AUP1G74GF 74AUP1G74GD 74AUP1G74GM 74AUP1G74GN 74AUP1G74GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
SD D CP SD D CP FF Q RD RD
001aah725
Q
Q S Q C1 1D R
001aah726
Fig 1.
74AUP1G74
Logic symbol
Fig 2.
IEC logic symbol
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Product data sheet
Rev. 5 -- 26 July 2010
2 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Q C
C C D
C
Q C RD C
SD
001aae087
CP
C C
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
74AUP1G74
CP 1 8 VCC
D
2
7
SD
74AUP1G74
Q CP D Q GND 1 2 3 4
001aae322
3
6
RD
8 7 6 5
VCC SD RD Q GND 4 5 Q
001aae323
Transparent top view
Fig 4.
Pin configuration SOT765-1
Fig 5.
Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203
74AUP1G74
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Product data sheet
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74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
74AUP1G74
terminal 1 index area SD 1 VCC 8
74AUP1G74
CP D Q GND 1 2 3 4 8 7 6 5 VCC
7
CP
RD SD RD Q Q
2
6
D
3 4
5
Q
GND
001aae324
001aai217
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2
Fig 7.
Pin configuration SOT902-1
6.2 Pin description
Table 3. Symbol Pin description Pin SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 CP D Q GND Q RD SD VCC 1 2 3 4 5 6 7 8 SOT902-1 7 6 5 4 3 2 1 8 clock input data input complement output ground (0 V) true output asynchronous reset input (active LOW) asynchronous set input (active LOW) supply voltage Description
7. Functional description
Table 4. Input SD L H L
[1]
Function table for asynchronous operation[1] Output RD H L L CP X X X D X X X Q H L H Q L H H
H = HIGH voltage level; L = LOW voltage level; X = don't care.
74AUP1G74
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Product data sheet
Rev. 5 -- 26 July 2010
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NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 5. Input SD H H
[1]
Function table for synchronous operation[1] Output RD H H CP D L H Qn+1 L H Qn+1 H L
H = HIGH voltage level; L = LOW voltage level; X = don't care; = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition.
8. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot
[1] [2]
Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation
Conditions VI < 0 V
[1]
Min -0.5 -50 -0.5 -50
[1]
Max +4.6 +4.6 +4.6 20 +50 +150 250
Unit V mA V mA V mA mA mA C mW
VO < 0 V Active mode and Power-down mode VO = 0 V to VCC
-0.5 -50 -65
Tamb = -40 C to +125 C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7. Symbol VCC VI VO Tamb t/V Operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 0.8 V to 3.6 V Active mode Power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 -40 Max 3.6 3.6 VCC 3.6 +125 200 Unit V V V V C ns/V
74AUP1G74
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Product data sheet
Rev. 5 -- 26 July 2010
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74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
10. Static characteristics
Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC CI CO input leakage current power-off leakage current additional power-off leakage current supply current additional supply current input capacitance output capacitance VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V; per pin VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V
[1]
Conditions
Min
Typ
Max -
Unit V V V V
0.70 x VCC 0.65 x VCC 1.6 2.0 VCC - 0.1 1.11 1.32 2.05 1.9 2.72 2.6 0.6 1.3
0.30 x VCC V 0.35 x VCC V 0.7 0.9 0.1 0.3 x VCC 0.31 0.31 0.31 0.44 0.31 0.44 0.1 0.2 0.2 0.5 40 V V V V V V V V V V V V V V V V V V A A A A A pF pF
0.75 x VCC -
74AUP1G74
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Product data sheet
Rev. 5 -- 26 July 2010
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74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 8. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +85 C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC input leakage current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V; per pin
[1]
Conditions
Min
Typ
Max -
Unit V V V V
0.70 x VCC 0.65 x VCC 1.6 2.0 VCC - 0.1 0.7 x VCC 1.03 1.30 1.97 1.85 2.67 2.55 -
0.30 x VCC V 0.35 x VCC V 0.7 0.9 0.1 0.3 x VCC 0.37 0.35 0.33 0.45 0.33 0.45 0.5 0.5 0.6 0.9 50 V V V V V V V V V V V V V V V V V V A A A A A
74AUP1G74
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 -- 26 July 2010
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74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 8. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +125 C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 0.8 V to 3.6 V IO = -1.1 mA; VCC = 1.1 V IO = -1.7 mA; VCC = 1.4 V IO = -1.9 mA; VCC = 1.65 V IO = -2.3 mA; VCC = 2.3 V IO = -3.1 mA; VCC = 2.3 V IO = -2.7 mA; VCC = 3.0 V IO = -4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF IOFF ICC ICC input leakage current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V; per pin
[1]
Conditions
Min
Typ
Max -
Unit V V V V
0.75 x VCC 0.70 x VCC 1.6 2.0 -
0.25 x VCC V 0.30 x VCC V 0.7 0.9 0.11 0.41 0.39 0.36 0.50 0.36 0.50 0.75 0.75 0.75 1.4 75 V V V V V V V V V V V V V V V V V A A A A A
VCC - 0.11 0.6 x VCC 0.93 1.17 1.77 1.67 2.40 2.30 -
0.33 x VCC V
[1]
One input at VCC - 0.6 V, other input at VCC or GND.
74AUP1G74
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 -- 26 July 2010
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NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
11. Dynamic characteristics
Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter Conditions Tamb = 25 C Min CL = 5 pF tpd propagation delay CP to Q, Q; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V SD to Q, Q; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V RD to Q, Q; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency CP; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 53 203 347 435 550 619 170 310 400 490 550 170 300 390 480 510 MHz MHz MHz MHz MHz MHz
[2] [2] [2]
Tamb = -40 C to +125 C Min Max (85 C) Min Max (125 C)
Unit
Typ[1]
Max
2.9 2.4 1.9 1.7 1.5 2.7 2.4 2.0 1.9 1.8 2.6 2.3 1.9 1.9 1.8
25.4 6.7 4.5 3.5 2.6 2.2 19.6 5.6 4.0 3.3 2.7 2.5 19.2 5.5 3.9 3.2 2.6 2.4
14.0 7.6 5.7 3.8 3.1 11.0 6.3 4.9 3.7 3.2 11.0 6.3 5.0 3.6 3.3
2.6 2.3 1.7 1.4 1.2 2.5 2.2 1.7 1.7 1.5 2.5 2.2 1.8 1.7 1.5
14.2 8.3 6.5 4.4 3.4 11.4 6.9 5.6 4.0 3.6 11.3 6.8 5.6 4.1 3.6
2.6 2.3 1.7 1.4 1.2 2.5 2.2 1.7 1.7 1.5 2.5 2.2 1.8 1.7 1.5
14.2 8.6 6.8 4.7 3.7 11.5 7.3 5.9 4.2 3.8 11.5 7.3 5.9 4.3 3.8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74AUP1G74
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 -- 26 July 2010
9 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter Conditions Tamb = 25 C Min CL = 10 pF tpd propagation delay CP to Q, Q; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V SD to Q, Q; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V RD to Q, Q; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency CP; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 52 192 324 421 486 550 150 280 310 370 410 150 230 250 360 360 MHz MHz MHz MHz MHz MHz
[2] [2] [2]
Tamb = -40 C to +125 C Min Max (85 C) Min Max (125 C)
Unit
Typ[1]
Max
3.1 2.7 2.5 2.0 1.8 2.9 2.7 2.6 2.3 2.2 2.8 2.6 2.5 2.2 2.0
28.9 7.5 5.1 4.1 3.2 2.8 23.2 6.5 4.6 3.9 3.2 3.0 22.7 6.4 4.5 3.3 3.2 2.9
15.8 8.7 6.5 4.6 3.8 12.9 7.5 5.6 4.4 3.9 12.8 7.5 5.8 4.4 4.0
2.9 2.4 2.2 1.8 1.6 2.8 2.3 2.3 2.0 1.9 2.7 2.3 2.3 2.0 1.9
16.1 9.4 7.2 5.3 4.1 13.3 7.9 6.3 4.8 4.2 13.2 8.1 6.3 4.9 4.3
2.9 2.4 2.2 1.8 1.6 2.8 2.3 2.3 2.0 1.9 2.7 2.3 2.3 2.0 1.9
16.1 9.8 7.6 5.6 4.4 13.5 8.3 6.6 5.2 4.4 13.4 8.4 6.7 5.2 4.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74AUP1G74
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 -- 26 July 2010
10 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter Conditions Tamb = 25 C Min CL = 15 pF tpd propagation delay CP to Q, Q; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V SD to Q, Q; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V RD to Q, Q; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency CP; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 50 181 301 407 422 481 120 190 240 300 320 120 160 190 270 300 MHz MHz MHz MHz MHz MHz
[2] [2] [2]
Tamb = -40 C to +125 C Min Max (85 C) Min Max (125 C)
Unit
Typ[1]
Max
3.5 3.2 2.7 2.4 2.2 3.3 3.2 2.8 2.8 2.5 3.2 3.1 2.7 2.6 2.4
32.4 8.3 5.6 4.6 3.6 3.2 26.7 7.3 5.2 4.3 3.7 3.5 26.1 7.2 5.1 4.3 3.6 3.4
17.6 9.5 7.2 5.2 4.4 14.7 8.3 6.4 5.1 4.6 14.5 8.4 6.5 5.0 4.6
3.3 2.8 2.5 2.2 2.0 3.1 2.9 2.5 2.2 2.4 3.1 2.7 2.6 2.4 2.3
17.8 10.5 8.1 5.8 4.9 15.2 9.0 7.1 5.5 5.0 15.0 9.2 7.3 5.5 5.0
3.3 2.8 2.5 2.2 2.0 3.1 2.9 2.5 2.2 2.4 3.1 2.7 2.6 2.4 2.3
18.0 11.1 8.6 6.2 5.2 15.4 9.5 7.5 5.8 5.2 15.2 9.7 7.7 5.8 5.2
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74AUP1G74
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 -- 26 July 2010
11 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter Conditions Tamb = 25 C Min CL = 30 pF tpd propagation delay CP to Q, Q; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V SD to Q, Q; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V RD to Q, Q; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency CP; see Figure 9 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 28 145 185 270 290 315 70 120 150 190 200 70 110 120 170 190 MHz MHz MHz MHz MHz MHz
[2] [2] [2]
Tamb = -40 C to +125 C Min Max (85 C) Min Max (125 C)
Unit
Typ[1]
Max
4.2 3.7 3.5 3.3 3.0 4.0 3.8 3.7 3.7 3.4 3.9 3.6 3.5 3.5 3.3
42.7 10.6 7.2 5.8 4.7 4.3 37.0 9.5 6.7 5.6 4.8 4.6 36.4 9.4 6.6 5.5 4.7 4.4
22.5 12.0 9.2 6.6 5.8 19.8 10.9 8.4 6.6 6.0 19.5 10.9 8.5 6.5 6.1
4.0 3.7 3.4 3.0 2.8 3.8 3.7 3.5 3.2 3.1 3.8 3.7 3.5 3.2 3.1
23.0 13.3 10.4 7.3 6.8 20.8 12.0 9.3 7.2 6.8 20.2 12.0 9.5 7.1 7.1
4.0 3.7 3.4 3.0 2.8 3.8 3.7 3.5 3.2 3.1 3.8 3.7 3.5 3.2 3.1
23.3 14.0 11.0 7.8 7.3 21.1 12.7 9.9 7.6 7.1 20.5 12.6 10.1 7.6 7.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74AUP1G74
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Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter Conditions Tamb = 25 C Min CL = 5 pF, 10 pF, 15 pF and 30 pF tsu set-up time D to CP HIGH; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V D to CP LOW; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V th hold time D to CP; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V trec recovery time RD; see Figure 9 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V SD; see Figure 9 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V -0.5 -0.4 -0.3 -0.2 -0.1 -0.3 -0.1 0 0.1 0.1 -0.3 -0.1 0 0.1 0.1 ns ns ns ns ns -0.5 -0.2 -0.2 -0.1 -0.1 -0.9 -0.6 -0.4 -0.1 -0.1 -0.9 -0.6 -0.4 -0.1 -0.1 ns ns ns ns ns -1.9 -0.3 -0.2 -0.2 -0.2 -0.2 0.5 0.2 0.1 0.1 0.1 0.5 0.2 0.1 0.1 0.1 ns ns ns ns ns ns 3.0 0.5 0.3 0.4 0.5 0.6 1.2 0.7 0.7 0.7 0.8 1.2 0.7 0.7 0.7 0.8 ns ns ns ns ns ns 3.4 0.6 0.3 0.4 0.2 0.3 1.2 0.6 0.5 0.4 0.4 1.2 0.6 0.5 0.4 0.4 ns ns ns ns ns ns Typ[1] Max Tamb = -40 C to +125 C Min Max (85 C) Min Max (125 C) Unit
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Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 9. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter Conditions Tamb = 25 C Min tW pulse width CP HIGH or LOW; see Figure 8 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V SD or RD LOW; see Figure 9 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V
[1] [2] [3] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs.
[3]
Tamb = -40 C to +125 C Min Max (85 C) Min Max (125 C)
Unit
Typ[1]
Max
-
2.1 1.1 0.9 0.6 0.6
-
2.7 1.5 1.6 1.7 1.9
-
2.7 1.5 1.6 1.7 1.9
-
ns ns ns ns ns
-
4.2 2.3 1.8 1.2 1.1
-
11.3 6.2 4.8 3.3 2.6
-
11.5 6.4 5.0 3.5 2.8
-
ns ns ns ns ns
-
2.8 2.9 3.0 3.0 3.5 3.9
-
-
-
-
-
pF pF pF pF pF pF
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Low-power D-type flip-flop with set and reset; positive-edge trigger
12. Waveforms
tW VI CP input GND 1/fmax VI D input GND th t su t PHL VOH Q output VOL VOH Q output VOL t PLH t PHL
001aae365
VM
VM
th t su t PLH
VM
VM
Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
The clock input (CP) to output (Q, Q) propagation delays, the data input (D) to clock input (CP) set-up and hold times and the clock input (CP) pulse width and maximum frequency Measurement points Output VM 0.5 x VCC Input VM 0.5 x VCC VI VCC tr = tf 3.0 ns
Table 10. VCC
Supply voltage 0.8 V to 3.6 V
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Low-power D-type flip-flop with set and reset; positive-edge trigger
VI CP input GND t rec VI SD input GND tW VI RD input GND t PLH VOH Q output VOL VOH Q output VOL t PHL t PLH
001aae366
VM
VM t rec tW
VM
t PHL
VM
VM
Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
The set input (SD) and reset input (RD) to output (Q, Q) propagation delays, the set input (SD) and reset input (RD) pulse widths and the reset input (RD) to clock input (CP) recovery time
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Low-power D-type flip-flop with set and reset; positive-edge trigger
VCC
VEXT
5 k
G
VI
VO
DUT
RT CL RL
001aac521
Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times Table 11. VCC 0.8 V to 3.6 V
[1]
Test data Load CL 5 pF, 10 pF, 15 pF and 30 pF RL
[1]
Supply voltage
VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ 2 x VCC 5 k or 1 M
For measuring enable and disable times RL = 5 k For measuring propagation delays, setup and hold times and pulse width RL = 1 M.
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Low-power D-type flip-flop with set and reset; positive-edge trigger
13. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
Fig 11. Package outline SOT765-1 (VSSOP8)
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Low-power D-type flip-flop with set and reset; positive-edge trigger
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
1
2
3
b 4 4x L
(2)
L1
e
8 e1
7 e1
6 e1
5
8x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07
Fig 12. Package outline SOT833-1 (XSON8)
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Low-power D-type flip-flop with set and reset; positive-edge trigger
XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm
E
SOT1089
terminal 1 index area
D
A A1
detail X
(4x)(2) e L (8x)(2) b4 5 e1
1 terminal 1 index area
8
L1 0 0.5 scale 1 mm
X
Dimensions Unit mm max nom min A(1) 0.5 A1 b D E e e1 L L1
0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.27 0.32 0.12 1.30 0.95
Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 References IEC JEDEC MO-252 JEITA European projection
sot1089_po
Issue date 10-04-09 10-04-12
Fig 13. Package outline SOT1089 (XSON8)
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Low-power D-type flip-flop with set and reset; positive-edge trigger
XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A1
detail X terminal 1 index area e1 L1
1
e
b
4
v w
M M
CAB C
C y1 C y
L2
L
8 5
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1
OUTLINE VERSION SOT996-2
REFERENCES IEC --JEDEC JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 07-12-18 07-12-21
Fig 14. Package outline SOT996-2 (XSON8U)
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Low-power D-type flip-flop with set and reset; positive-edge trigger
XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D terminal 1 index area
B
A
E
A A1
detail X
L1 L
e
4
e v M C A B w M C
5
C y1 C y
3
metal area not for soldering
2 6
b
e1
e1
7 1
terminal 1 index area
8
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05
OUTLINE VERSION SOT902-1
REFERENCES IEC --JEDEC MO-255 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-11-25 07-11-14
Fig 15. Package outline SOT902-1 (XQFN8U)
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Low-power D-type flip-flop with set and reset; positive-edge trigger
XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm
SOT1116
1
2
3
b 4
(4x)(2)
L1 e
L
8 e1
7 e1
6 e1
5
(8x)(2) A1 A
D
E
terminal 1 index area
0 Dimensions Unit mm A(1) A1 b D E e e1 0.3 L L1
0.5 scale
1 mm
max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95
0.35 0.40 0.30 0.35 0.27 0.32
Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1116 References IEC JEDEC JEITA European projection
sot1116_po
Issue date 10-04-02 10-04-07
Fig 16. Package outline SOT1116 (XSON8)
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Low-power D-type flip-flop with set and reset; positive-edge trigger
XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
b 1 2 3 4 (4x)(2)
L1 e
L
8 e1
7 e1
6 e1
5
(8x)(2) A1 A
D
E
terminal 1 index area
0 Dimensions Unit mm A(1) A1 b D E e e1 L L1
0.5 scale
1 mm
max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32
Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1203 References IEC JEDEC JEITA European projection
sot1203_po
Issue date 10-04-02 10-04-06
Fig 17. Package outline SOT1203 (XSON8)
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Low-power D-type flip-flop with set and reset; positive-edge trigger
14. Abbreviations
Table 12. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model
15. Revision history
Table 13. Revision history Release date 20100726 Data sheet status Product data sheet Change notice Supersedes 74AUP1G74 v.4 Document ID 74AUP1G74 v.5 Modifications:
* * *
Added type number 74AUP1G74GF (SOT1089/XSON8 package). Added type number 74AUP1G74GN (SOT1116/XSON8 package). Added type number 74AUP1G74GS (SOT1203/XSON8 package). Product data sheet Product data sheet Product data sheet Product data sheet 74AUP1G74 v.3 74AUP1G74 v.2 74AUP1G74 v.1 -
74AUP1G74 v.4 74AUP1G74 v.3 74AUP1G74 v.2 74AUP1G74 v.1
20080603 20080207 20070515 20060825
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Low-power D-type flip-flop with set and reset; positive-edge trigger
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be
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Low-power D-type flip-flop with set and reset; positive-edge trigger
Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Low-power D-type flip-flop with set and reset; positive-edge trigger
18. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Contact information. . . . . . . . . . . . . . . . . . . . . 27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 July 2010 Document identifier: 74AUP1G74

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